The reading assignments are from chapters in the course textbook: Rabaey, Jan, Anantha Chandrakasan, and Bora Nikolic. Digital Integrated Circuits: A Design Perspective. 2nd ed. Upper Saddle River, NJ: Prentice Hall, 2002. ISBN: 0130909963.
| LEC # | TOPICS | READINGS |
|---|---|---|
| 1 |
Challenges in Digital IC Design Course Overview |
1 |
| 2 |
CMOS Inverter I MOS Device Model with Sub-micron Effects VTC Parameters - DC Characteristics |
3.1-3.3, 5.1-5.3 |
| 3 |
CMOS Inverter II CMOS Propagation Delay Parasitic Capacitance Estimation Layout of an Inverter Supply and Threshold Voltage Scaling SPICE Simulation Techniques |
5.4.1, 5.4.2 |
| Tutorial on Design Tools - Layout of a CMOS Gate, Extraction, SPICE, IRSIM | ||
| 4 |
CMOS Inverter III Components of Energy and Power Switching, Short-Circuit and Leakage Components SPICE Simulation Techniques |
5.5 |
| 5 |
Combinational Logic I Static CMOS Construction Ratioed Logic |
6.1, 6.2.1 (pp. 237-251), 6.2.2 |
| 6 |
Combinational Logic II Pass Transistor / Transmission Gate Logic DCVSL Introduction to Dynamic Logic |
6.2.3 |
| 7 |
Combinational Logic III Dynamic Logic Design Considerations Power Dissipation in CMOS |
6.3 |
| 8 |
Combinational Logic IV Power Consumption in CMOS Logic (cont.) Leakage Power Dissipation Logical Effort Sizing - Performance Optimization of Digital Circuits |
pp. 251-263, 6.4 |
| 9 |
Arithmetic Structures / Bit Slice Design Adders, Multipliers, Shifters Design Methodology Layout Techniques and Mapping Project Schedule and Guidelines |
11.1-11.6, 8 |
| 10 |
Evening Session on Exploring Project Ideas Finish Arithmetic Structures and Project Ideas |
|
| 11 |
Guest Lecture by Prof. Tayo Akinwande Integrated CMOS Processing |
2 |
| 12 |
Sequential Circuits I Classification / Parameters Static Latches and Register |
7.1, 7.2 |
| 13 |
Sequential Circuits II Race Condition Dynamic Latches and Registers Two Phase vs. Single Phase |
7.3 |
|
Quiz #1 Covers Inverter, Combinational Logic |
||
| 14 |
Sequential Circuits: III Pulse Based Registers Latch vs. Register Systems Metastability |
7.4-7.8, 10.3.4, 10.5.1 |
| 15 |
Interconnect Capacitance Estimation Buffer Chains Low Swing Drivers Power Distribution |
4.1-4.3, 4.4.1-4.4.4, 9 |
| 16 |
Interconnect (cont.) Issues in Timing - Impact of Clock Skew and Jitter |
9, 10.1, 10.2 |
| 17 |
Clock Distribution Origins of Clock Skew / Jitter and Impact on Performance Clock Distribution Techniques Self-timed Circuits |
10.3.1-10.3.3, 10.4 |
| 18 |
Memory I: ROM / EPROM / PLA Design Organization / Architecture Cell Design Sense-amplifiers PLA folding techniques Self-timing |
12 |
| 19 |
Memory II: SRAM Design Cell Design Differential Sense Amplifiers Self-timing |
|
| 20 |
Memory III DRAM Design Single Ended Sense Amplifier CMOS Scaling |
|
|
Quiz #2 Covers Arithmetic Structures, Inter-connect, Sequential Circuits and Memory |
||
| 21 |
Advanced Voltage Scaling Techniques DC-DC Converter Design Performance Feedback Dynamic Voltage / Frequency Scaling |
11.7 |
| 22 |
Power Reduction Through Switching Activity Reduction Testing in VLSI Defects, Fault Models, Path Sensitization Scan, Built-in-self Test, IDDQ |
Insert H |
| 23 | Presentation of Final Projects | |
| 24 | Presentation of Final Projects (cont.) |