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The Beta is an example of
a reduced-instruction-set

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computer (RISC) architecture.

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“Reduced” refers to the
fact that in the Beta ISA,

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most instructions only
access the internal registers

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for their operands
and destination.

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Memory values are
loaded and stored

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using separate memory-access
instructions, which

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implement only a simple
address calculation.

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These reductions
lead to smaller,

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higher-performance hardware
implementations and simpler

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compilers on the software side.

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The ARM and MIPS ISAs are other
examples of RISC architectures.

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Intel’s x86 ISA is more complex.

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There is a limited amount of
storage inside of the CPU —

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using the language
of sequential logic,

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we’ll refer to this
as the CPU state.

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There’s a 32-bit program counter
(PC for short) that holds

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the address of the current
instruction in main memory.

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And there are
thirty-two registers,

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numbered 0 through 31.

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Each register holds
a 32-bit value.

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We’ll use use 5-bit fields
in the instruction to specify

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the number of the register to be
used an operand or destination.

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As shorthand, we’ll refer to a
register using the prefix “R”

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followed by its number, e.g.,
“R0” refers to the register

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selected by the
5-bit field 0b00000.

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Register 31 (R31) is special
— its value always reads as 0

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and writes to R31 have
no affect on its value.

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The number of bits
in each register

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and hence the number of bits
supported by ALU operations

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is a fundamental
parameter of the ISA.

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The Beta is a
32-bit architecture.

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Many modern computers
are 64-bit architectures,

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meaning they have
64-bit registers

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and a 64-bit datapath.

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Main memory is an
array of 32-bit words.

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Each word contains
four 8-bit bytes.

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The bytes are
numbered 0 through 3,

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with byte 0 corresponding
to the low-order 7 bits

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of the 32-bit value, and so on.

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The Beta ISA only
supports word accesses,

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either loading or storing
full 32-bit words.

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Most “real” computers also
support accesses to bytes

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and half-words.

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Even though the Beta only
accesses full words, following

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a convention used by many
ISAs it uses byte addresses.

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Since there are 4
bytes in each word,

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consecutive words in memory
have addresses that differ by 4.

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So the first word in
memory has address 0,

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the second word
address 4, and so on.

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You can see the addresses to
left of each memory location

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in the diagram shown here.

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Note that we’ll usually use
hexadecimal notation when

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specifying addresses and other
binary values — the “0x” prefix

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indicates when a
number is in hex.

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When drawing a memory diagram,
we’ll follow the convention

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that addresses increase as
you read from top to bottom.

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The Beta ISA supports
32-bit byte addressing,

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so an address fits exactly into
one 32-bit register or memory

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location.

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The maximum memory size is 2^32
bytes or 2^30 words — that’s 4

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gigabytes (4 GB) or one
billion words of main memory.

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Some Beta implementations
might actually

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have a smaller
main memory, i.e.,

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one with fewer than
1 billion locations.

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Why have separate
registers and main memory?

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Well, modern programs and
datasets are very large,

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so we’ll want to have a large
main memory to hold everything.

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But large memories are slow
and usually only support access

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to one location at a time, so
they don’t make good storage

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for use in each instruction
which needs to access several

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operands and store a result.

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If we used only one
large storage array,

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then an instruction would need
to have three 32-bit addresses

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to specify the two source
operands and destination — each

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instruction encoding
would be huge!

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And the required memory
accesses would have to be

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one-after-the-other, really
slowing down instruction

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execution.

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On the other hand, if we use
registers to hold the operands

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and serve as the
destination, we can

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design the register
hardware for parallel access

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and make it very fast.

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To keep the speed up we won’t
be able to have very many

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registers — a classic
size-vs-speed performance

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tradeoff we see in digital
systems all the time.

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In the end, the tradeoff
leading to the best performance

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is to have a small number
of very fast registers used

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by most instructions and a
large but slow main memory.

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So that’s what
the BETA ISA does.

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In general, all program data
will reside in main memory.

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Each variable used by the
program “lives” in a specific

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main memory location and so
has a specific memory address.

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For example, in
the diagram below,

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the value of variable “x”
is stored in memory location

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0x1008, and the value of “y”
is stored in memory location

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0x100C, and so on.

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To perform a computation,
e.g., to compute x*37 and store

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the result in y, we would have
to first load the value of x

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into a register, say, R0.

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Then we would have the datapath
multiply the value in R0

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by 37, storing the
result back into R0.

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Here we’ve assumed that
the constant 37 is somehow

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available to the datapath
and doesn’t itself need to be

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loaded from memory.

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Finally, we would
write the updated value

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in R0 back into memory
at the location for y.

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Whew!

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A lot of steps…

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Of course, we
could avoid all the

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loading and storing if we chose
to keep the values for x and y

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in registers.

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Since there are
only 32 registers,

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we can’t do this for
all of our variables,

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but maybe we could arrange to
load x and y into registers,

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do all the required computations
involving x and y by referring

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to those registers, and
then, when we’re done,

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store changes to x and y back
into memory for later use.

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Optimizing performance by
keeping often-used values

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in registers is a favorite trick
of programmers and compiler

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writers.

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So the basic program
template is some loads

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to bring values into
the registers, followed

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by computation, followed
by any necessary stores.

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ISAs that use this template
are usually referred

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to as “load-store
architectures”.