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6.004 students work around the dryer bottleneck
by finding a laundromat that has two dryers

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for every washer.

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Looking at the timeline you can see the plan,
which is divided into 30-minute steps.

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The washer is in use every step, producing
a newly-washed load every 30 minutes.

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Dryer usage is interleaved, where Dryer #1
is used to dry the odd-numbered loads and

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Dryer #2 is used to dry the even-numbered
loads.

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Once started, a dryer runs for a duration
of two steps, a total of 60 minutes.

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Since the dryers run on a staggered schedule,
the system as a whole produces a load of clean,

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dry laundry every 30 minutes.

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The steady-state throughput is 1 load of laundry
every 30 minutes and the latency for a particular

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load of laundry is 90 minutes.

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And now here's the take-home message from
this example.

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Consider the operation of the two-dryer system.

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Even though the component dryers themselves
aren't pipelined, the two-dryer interleaving

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system is acting like a 2-stage pipeline with
a clock period of 30 minutes and a latency

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of 60 minutes.

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In other words, by interleaving the operation
of 2 unpipelined components we can achieve

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the effect of a 2-stage pipeline.

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Returning to the example of the previous section,
we couldn't improve the throughput of our

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pipelined system past 1/8 ns because the minimum
clock period was set by the 8 ns latency of

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the C module.

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To improve the throughput further we either
need to find a pipelined version of the C

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component or use an interleaving strategy
to achieve the effect of a 2-stage pipeline

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using two instances of the unpipelined C component.

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Let's try that…

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Here's a circuit for a general-purpose two-way
interleaver, using, in this case, two copies

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of the unpipelined C component, C_0 and C_1.

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The input for each C component comes from
a D-latch, which has the job of capturing

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and holding the input value.

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There's also a multiplexer to select which
C-component output will be captured by the

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output register.

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In the lower left-hand corner of the circuit
is a very simple 2-state FSM with one state

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bit.

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The next-state logic is a single inverter,
which causes the state to alternate between

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0 and 1 on successive clock cycles.

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This timing diagram shows how the state bit
changes right after each rising clock edge.

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To help us understand the circuit, we'll look
at some signal waveforms to illustrate its

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operation.

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To start, here are the waveforms for the CLK
signal and our FSM state bit from the previous

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slide.

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A new X input arrives from the previous stage
just after the rising edge of the clock.

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Next, let's follow the operation of the C_0
component.

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Its input latch is open when FSM Q is low,
so the newly arriving X_1 input passes through

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the latch and C_0 can begin its computation,
producing its result at the end of clock cycle

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#2.

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Note that the C_0 input latch closes at the
beginning of the second clock cycle, holding

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the X_1 input value stable even though the
X input is starting to change.

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The effect is that C_0 has a valid and stable
input for the better part of 2 clock cycles

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giving it enough time to compute its result.

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The C_1 waveforms are similar, just shifted
by one clock cycle.

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C_1's input latch is open when FSM Q is high,
so the newly arriving X_2 input passes through

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the latch and C_1 can begin its computation,
producing its result at the end of clock cycle

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#3.

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Now let's check the output of the multiplexer.

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When FSM Q is high, it selects the value from
C_0 and when FSM Q is low, it selects the

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value from C_1.

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We can see that happening in the waveform
shown.

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Finally, at the rising edge of the clock,
the output register captures the value on

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its input and holds it stable for the remainder
of the clock cycle.

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The behavior of the interleaving circuit is
like a 2-stage pipeline: the input value arriving

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in cycle i is processed over two clock cycles
and the result output becomes available on

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cycle i+2.

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What about the clock period for the interleaving
system?

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Well, there is some time lost to the propagation
delays of the upstream pipeline register that

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supplies the X input, the internal latches
and multiplexer, and the setup time of the

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output register.

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So the clock cycle has to be just a little
bit longer than half the propagation delay

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of the C module.

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We can treat the interleaving circuit as a
2-stage pipeline, consuming an input value

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every clock cycle and producing a result two
cycles later.

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When incorporating an N-way interleaved component
in our pipeline diagrams, we treat it just

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like a N-stage pipeline.

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So N of our pipelining contours have to pass
through the component.

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Here we've replaced the slow unpipelined C
component with a 2-way interleaved C-prime

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component.

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We can follow our process for drawing pipeline
contours.

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First we draw a contour across all the outputs.

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Then we add contours, ensuring that two of
them pass through the C-prime component.

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Then we add pipeline registers at the intersections
of the contours with the signal connections.

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We see that the contours passing through C-prime
have caused extra pipeline registers to be

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added on the other inputs to the F module,
accommodating the 2-cycle delay through C-prime.

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Somewhat optimistically we've specified the
C-prime minimum t_CLK to be 4 ns, so that

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means that the slow component which determines
the system's clock period is now the F module,

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with a propagation delay of 5 ns.

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So the throughput of our new pipelined circuit
is 1 output every 5 ns, and with 5 contours,

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it's a 5-pipeline so the latency is 5 times
the clock period or 25 ns.

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By running pipelined systems in parallel we
can continue to increase the throughput.

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Here we show a laundry with 2 washers and
4 dryers, essentially just two copies of the

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1-washer, 2-dryer system shown earlier.

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The operation is as described before, except
that at each step the system produces and

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consumes two loads of laundry.

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So the throughput is 2 loads every 30 minutes
for an effective rate of 1 load every 15 minutes.

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The latency for a load hasn't changed; it's
still 90 minutes per load.

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We've seen that even with slow components
we can use interleaving and parallelism to

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continue to increase throughput.

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Is there an upper bound on the throughput
we can achieve?

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Yes!

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The timing overhead of the pipeline registers
and interleaving components will set a lower

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bound on the achievable clock period, thus
setting an upper bound on the achievable throughput.

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Sorry, no infinite speed-up is possible in
the real world.