1 00:00:00,859 --> 00:00:05,870 Earlier we talked about about finding equivalent FSMs with fewer states. 2 00:00:05,870 --> 00:00:10,910 Now we'll develop an approach for finding such FSMs by looking for two states that that 3 00:00:10,910 --> 00:00:16,610 can be merged into a single state without changing the behavior of the FSM in any externally 4 00:00:16,610 --> 00:00:19,680 distinguishable manner. 5 00:00:19,680 --> 00:00:23,490 Two states are equivalent if they meet the following two criteria. 6 00:00:23,490 --> 00:00:27,800 First, the states must have identical outputs. 7 00:00:27,800 --> 00:00:32,710 This makes sense: the outputs are visible to the outside, so if their values differed 8 00:00:32,710 --> 00:00:38,030 between the two states, that difference would clearly be externally distinguishable! 9 00:00:38,030 --> 00:00:46,600 Second, for each combination of input values, the two states transition to equivalent states. 10 00:00:46,600 --> 00:00:51,100 Our strategy for deriving an equivalent machine with fewer states will be to start with our 11 00:00:51,100 --> 00:00:57,100 original FSM, find pairs of equivalent states and merge those states. 12 00:00:57,100 --> 00:01:02,950 We'll keep repeating the process until we can't find any more equivalent states. 13 00:01:02,950 --> 00:01:05,640 Let's try this on our ant FSM. 14 00:01:05,640 --> 00:01:09,250 First we need to find a pair of states that have the same outputs. 15 00:01:09,250 --> 00:01:14,110 As it turns out, there's only one such pair: WALL1 and CORNER, both of which assert the 16 00:01:14,110 --> 00:01:16,520 turn-right and forward outputs. 17 00:01:16,520 --> 00:01:22,600 Okay, so let's assume that WALL1 and CORNER are equivalent and ask if they transition 18 00:01:22,600 --> 00:01:28,770 to equivalent states for each applicable combination of input values. 19 00:01:28,770 --> 00:01:34,158 For these two states, all the transitions depend only on the value of the R input, so 20 00:01:34,158 --> 00:01:37,100 we just have to check two cases. 21 00:01:37,100 --> 00:01:40,000 If R is 0, both states transition to CORNER. 22 00:01:40,000 --> 00:01:44,930 If R is 1, both states transition to WALL2. 23 00:01:44,930 --> 00:01:50,270 So both equivalence criteria are satisfied and we can conclude that the WALL1 and CORNER 24 00:01:50,270 --> 00:01:53,810 states are equivalent and can be merged. 25 00:01:53,810 --> 00:01:58,658 This gives us the four-state FSM shown here, where we've called the single merged state 26 00:01:58,658 --> 00:02:00,600 WALL1. 27 00:02:00,600 --> 00:02:06,950 This smaller, equivalent FSM behaves exactly as the previous 5-state FSM. 28 00:02:06,950 --> 00:02:11,840 The implementation of the 5-state machine requires 3 state bits; the implementation 29 00:02:11,840 --> 00:02:16,040 of the 4-state machine only requires 2 state bits. 30 00:02:16,040 --> 00:02:20,780 Reducing the number of state bits by 1 is huge since it reduces the size of the required 31 00:02:20,780 --> 00:02:23,680 ROM by half! 32 00:02:23,680 --> 00:02:29,180 Just as we were able to achieve considerable hardware savings by minimizing Boolean equations, 33 00:02:29,180 --> 00:02:34,590 we can do the same in sequential logic by merging equivalent states. 34 00:02:34,590 --> 00:02:38,760 Roboant customers are looking forward to the price cut! 35 00:02:38,760 --> 00:02:43,810 Let's look at what we'd need to do if we wanted to implement the FSM using logic gates instead 36 00:02:43,810 --> 00:02:47,490 a ROM for the combinational logic. 37 00:02:47,490 --> 00:02:52,349 First we have to build the truth table, entering all the transitions in the state transition 38 00:02:52,349 --> 00:02:53,629 diagram. 39 00:02:53,629 --> 00:02:55,260 We'll start with the LOST state. 40 00:02:55,260 --> 00:02:59,910 So if the FSM is in this state, the F output should be 1. 41 00:02:59,910 --> 00:03:05,420 If both antenna inputs are 0, the next state is also LOST. 42 00:03:05,420 --> 00:03:09,950 Assigning the LOST state the encoding 00, we've captured this information in the first 43 00:03:09,950 --> 00:03:12,660 row of the table. 44 00:03:12,660 --> 00:03:19,069 If either antenna is touching, the FSM should transition from LOST to the rotate-counterclockwise 45 00:03:19,069 --> 00:03:20,069 state. 46 00:03:20,069 --> 00:03:24,590 We've given this an encoding of 01. 47 00:03:24,590 --> 00:03:29,790 There are three combinations of L and R values that match this transition, so we've added 48 00:03:29,790 --> 00:03:32,329 three rows to the truth table. 49 00:03:32,329 --> 00:03:36,659 This takes care of all the transitions from the LOST state. 50 00:03:36,659 --> 00:03:41,530 Now we can tackle the transitions from the rotate-counterclockwise state. 51 00:03:41,530 --> 00:03:46,530 If either antenna is touching, the next state is again rotate-counterclockwise. 52 00:03:46,530 --> 00:03:50,819 So we've identified the matching values for the inputs and added the appropriate three 53 00:03:50,819 --> 00:03:53,560 rows to the transition table. 54 00:03:53,560 --> 00:03:59,980 We can continue in a similar manner to encode the transitions one-by-one. 55 00:03:59,980 --> 00:04:06,400 Here's the final table, where we've used don't cares to reduce the number of rows for presentation. 56 00:04:06,400 --> 00:04:10,530 Next we want to come up with Boolean equations for each of the outputs of the combinational 57 00:04:10,530 --> 00:04:16,310 logic, i.e., the two next-state bits and the three motion-control outputs. 58 00:04:16,310 --> 00:04:21,728 Here are the Karnaugh maps for the two next-state bits. 59 00:04:21,728 --> 00:04:28,409 Using our K-map skills from Chapter 4, we'll find a cover of the prime implicants for S1-prime 60 00:04:28,409 --> 00:04:33,990 and write down the corresponding product terms in a minimal sum-of-products equation. 61 00:04:33,990 --> 00:04:37,490 And then do the same for the other next-state bit. 62 00:04:37,490 --> 00:04:41,909 We can follow a similar process to derive minimal sum-of-products expressions for the 63 00:04:41,909 --> 00:04:44,650 motion-control outputs. 64 00:04:44,650 --> 00:04:49,710 Implementing each sum-of-products in a straight-forward fashion with AND and OR gates, we get the 65 00:04:49,710 --> 00:04:52,470 following schematic for the ant brain. 66 00:04:52,470 --> 00:04:53,680 Pretty neat! 67 00:04:53,680 --> 00:04:58,949 Who knew that maze following behavior could be implemented with a couple of D registers 68 00:04:58,949 --> 00:05:02,910 and a handful of logic gates? 69 00:05:02,910 --> 00:05:08,030 There are many complex behaviors that can be created with surprisingly simple FSMs. 70 00:05:08,030 --> 00:05:14,110 Early on, the computer graphics folks learned that group behaviors like swarming, flocking 71 00:05:14,110 --> 00:05:18,899 and schooling can be modeled by equipping each participant with a simple FSM. 72 00:05:18,899 --> 00:05:24,070 So next time you see the massive battle scene from the Lord of the Rings movie, think of 73 00:05:24,070 --> 00:05:27,710 many FSMs running in parallel! 74 00:05:27,710 --> 00:05:32,469 Physical behaviors that arise from simple interactions between component molecules can 75 00:05:32,469 --> 00:05:36,930 sometimes be more easily modeled using cellular automata - 76 00:05:36,930 --> 00:05:42,520 arrays of communicating FSMS - than by trying to solve the partial differential equations 77 00:05:42,520 --> 00:05:46,710 that model the constraints on the molecules' behavior. 78 00:05:46,710 --> 00:05:52,900 And here's an idea: what if we allowed the FSM to modify its own transition table? 79 00:05:52,900 --> 00:05:54,279 Hmm. 80 00:05:54,279 --> 00:05:57,689 Maybe that's a plausible model for evolution! 81 00:05:57,689 --> 00:05:59,949 FSMs are everywhere! 82 00:05:59,949 --> 00:06:02,400 You'll see FSMs for the rest of your lifeā€¦