1 00:00:01,130 --> 00:00:05,610 In the last lecture we learned how to build combinational logic circuits given a functional 2 00:00:05,610 --> 00:00:10,760 specification that told us how output values were related to the current values of the 3 00:00:10,760 --> 00:00:12,290 inputs. 4 00:00:12,290 --> 00:00:16,550 But here's a simple device we can't build with combinational logic. 5 00:00:16,550 --> 00:00:20,960 The device has a light that serves as the output and push button that serves as the 6 00:00:20,960 --> 00:00:22,029 input. 7 00:00:22,029 --> 00:00:26,359 If the light is off and we push the button, the light turns on. 8 00:00:26,359 --> 00:00:31,599 If the light is on and we push the button, the light turns off. 9 00:00:31,599 --> 00:00:35,340 What makes this circuit different from the combinational circuits we've discussed so 10 00:00:35,340 --> 00:00:36,770 far? 11 00:00:36,770 --> 00:00:41,890 The biggest difference is that the device's output is not function of the device's *current* 12 00:00:41,890 --> 00:00:43,660 input value. 13 00:00:43,660 --> 00:00:48,240 The behavior when the button is pushed depends on what has happened in the past: 14 00:00:48,240 --> 00:00:55,010 odd numbered pushes turn the light on, even numbered pushes turn the light off. 15 00:00:55,010 --> 00:00:59,861 The device is "remembering" whether the last push was an odd push or an even push so it 16 00:00:59,861 --> 00:01:05,409 will behave according to the specification when the next button push comes along. 17 00:01:05,409 --> 00:01:11,759 Devices that remember something about the history of their inputs are said to have state. 18 00:01:11,759 --> 00:01:14,049 The second difference is more subtle. 19 00:01:14,049 --> 00:01:20,039 The push of the button marks an event in time: we speak of the state before the push ("the 20 00:01:20,039 --> 00:01:25,329 light is on") and state after the push ("the light is off"). 21 00:01:25,329 --> 00:01:30,479 It's the transition of the button from un-pushed to pushed that we're interested in, not the 22 00:01:30,479 --> 00:01:32,549 whether the button is currently pushed or not. 23 00:01:32,549 --> 00:01:39,939 The device's internal state is what allows it to produce different outputs even though 24 00:01:39,939 --> 00:01:42,090 it receives the same input. 25 00:01:42,090 --> 00:01:47,030 A combinational device can't exhibit this behavior since its outputs depends only on 26 00:01:47,030 --> 00:01:49,939 the current values of the input. 27 00:01:49,939 --> 00:01:55,670 Let's see how we'll incorporate the notion of device state into our circuitry. 28 00:01:55,670 --> 00:01:59,880 We'll introduce a new abstraction of a memory component that will store the current state 29 00:01:59,880 --> 00:02:02,789 of the digital system we want to build. 30 00:02:02,789 --> 00:02:08,038 The memory component stores one or more bits that encode the current state of the system. 31 00:02:08,038 --> 00:02:13,170 These bits are available as digital values on the memory component's outputs, shown here 32 00:02:13,170 --> 00:02:16,890 as the wire marked "Current State". 33 00:02:16,890 --> 00:02:21,640 The current state, along with the current input values, are the inputs to a block of 34 00:02:21,640 --> 00:02:25,900 combinational logic that produces two sets of outputs. 35 00:02:25,900 --> 00:02:30,220 One set of outputs is the next state of the device, encoded using the same number of bits 36 00:02:30,220 --> 00:02:32,590 as the current state. 37 00:02:32,590 --> 00:02:38,310 The other set of outputs are the signals that serve as the outputs of the digital system. 38 00:02:38,310 --> 00:02:43,500 The functional specification for the combinational logic (perhaps a truth table, or maybe a set 39 00:02:43,500 --> 00:02:48,350 of Boolean equations) specifies how the next state and system outputs 40 00:02:48,350 --> 00:02:53,520 are related to the current state and current inputs. 41 00:02:53,520 --> 00:02:59,540 The memory component has two inputs: a LOAD control signal that indicates when to replace 42 00:02:59,540 --> 00:03:04,320 the current state with the next state, and a data input that specifies what the next 43 00:03:04,320 --> 00:03:06,610 state should be. 44 00:03:06,610 --> 00:03:11,500 Our plan is to periodically trigger the LOAD control, which will produce a sequence of 45 00:03:11,500 --> 00:03:13,790 values for the current state. 46 00:03:13,790 --> 00:03:18,250 Each state in the sequence is determined from the previous state and the inputs at the time 47 00:03:18,250 --> 00:03:21,460 the LOAD was triggered. 48 00:03:21,460 --> 00:03:25,980 Circuits that include both combinational logic and memory components are called sequential 49 00:03:25,980 --> 00:03:27,829 logic. 50 00:03:27,829 --> 00:03:31,930 The memory component has a specific capacity measured in bits. 51 00:03:31,930 --> 00:03:37,350 If the memory component stores K bits, that puts an upper bound of 2^K on the number of 52 00:03:37,350 --> 00:03:43,310 possible states since the state of the device is encoded using the K bits of memory. 53 00:03:43,310 --> 00:03:48,290 So, we'll need to figure out how to build a memory component that can loaded with new 54 00:03:48,290 --> 00:03:50,350 values now and then. 55 00:03:50,350 --> 00:03:52,060 That's the subject of this chapter. 56 00:03:52,060 --> 00:03:57,710 We'll also need a systematic way of designing sequential logic to achieve the desired sequence 57 00:03:57,710 --> 00:03:59,130 of actions. 58 00:03:59,130 --> 00:04:02,310 That's the subject of the next chapter. 59 00:04:02,310 --> 00:04:06,370 We've been representing bits as voltages, so we might consider using a capacitor to 60 00:04:06,370 --> 00:04:08,730 store a particular voltage. 61 00:04:08,730 --> 00:04:11,900 The capacitor is passive two-terminal device. 62 00:04:11,900 --> 00:04:16,910 The terminals are connected to parallel conducting plates separated by insulator. 63 00:04:16,910 --> 00:04:21,510 Adding charge Q to one plate of the capacitor generates a voltage difference V between the 64 00:04:21,510 --> 00:04:23,280 two plate terminals. 65 00:04:23,280 --> 00:04:31,370 Q and V are related by the capacitance C of the capacitor: Q = CV. 66 00:04:31,370 --> 00:04:36,340 When we add charge to a capacitor by hooking a plate terminal to higher voltage, that's 67 00:04:36,340 --> 00:04:38,060 called "charging the capacitor". 68 00:04:38,060 --> 00:04:42,221 And when we take away charge by connecting the plate terminal to a lower voltage, that's 69 00:04:42,221 --> 00:04:45,380 called "discharging the capacitor". 70 00:04:45,380 --> 00:04:50,610 So here's how a capacitor-based memory device might work. 71 00:04:50,610 --> 00:04:54,389 One terminal of the capacitor is hooked to some stable reference voltage. 72 00:04:54,389 --> 00:04:59,470 We'll use an NFET switch to connect the other plate of the capacitor to a wire called the 73 00:04:59,470 --> 00:05:00,770 bit line. 74 00:05:00,770 --> 00:05:05,060 The gate of the NFET switch is connected to a wire called the word line. 75 00:05:05,060 --> 00:05:09,710 To write a bit of information into our memory device, drive the bit line to the desired 76 00:05:09,710 --> 00:05:14,820 voltage (i.e., a digital 0 or a digital 1). 77 00:05:14,820 --> 00:05:19,100 Then set the word line HIGH, turning on the NFET switch. 78 00:05:19,100 --> 00:05:24,740 The capacitor will then charge or discharge until it has the same voltage as the bit line. 79 00:05:24,740 --> 00:05:30,440 At this point, set the word line LOW, turning off the NFET switch and isolating the capacitor's 80 00:05:30,440 --> 00:05:33,250 charge on the internal plate. 81 00:05:33,250 --> 00:05:36,930 In a perfect world, the charge would remain on the capacitor's plate indefinitely. 82 00:05:36,930 --> 00:05:43,700 At some later time, to access the stored information, we first charge the bit line to some intermediate 83 00:05:43,700 --> 00:05:44,970 voltage. 84 00:05:44,970 --> 00:05:49,780 Then set the word line HIGH, turning on the NFET switch, which connects the charge on 85 00:05:49,780 --> 00:05:52,940 the bit line to the charge on the capacitor. 86 00:05:52,940 --> 00:05:56,830 The charge sharing between the bit line and capacitor will have some small effect on the 87 00:05:56,830 --> 00:06:00,610 charge on the bit line and hence its voltage. 88 00:06:00,610 --> 00:06:05,190 If the capacitor was storing a digital 1 and hence was at a higher voltage, 89 00:06:05,190 --> 00:06:11,639 charge will flow from the capacitor into the bit line, raising the voltage of the bit line. 90 00:06:11,639 --> 00:06:16,180 If the capacitor was storing a digital 0 and was at lower voltage, charge will flow from 91 00:06:16,180 --> 00:06:20,620 the bit line into the capacitor, lowering the voltage of the bit line. 92 00:06:20,620 --> 00:06:25,870 The change in the bit line's voltage depends on the ratio of the bit line capacitance to 93 00:06:25,870 --> 00:06:30,710 C, the storage capacitor's capacitance, but is usually quite small. 94 00:06:30,710 --> 00:06:37,360 A very sensitive amplifier, called a sense amp, is used to detect that small change and 95 00:06:37,360 --> 00:06:42,730 produce a legal digital voltage as the value read from the memory cell. 96 00:06:42,730 --> 00:06:44,210 Whew! 97 00:06:44,210 --> 00:06:49,090 Reading and writing require a whole sequence of operations, along with carefully designed 98 00:06:49,090 --> 00:06:51,690 analog electronics. 99 00:06:51,690 --> 00:06:56,420 The good news is that the individual storage capacitors are quite small. 100 00:06:56,420 --> 00:07:01,240 In modern integrated circuits we can fit billions of bits of storage on relatively inexpensive 101 00:07:01,240 --> 00:07:05,340 chips called dynamic random-access memories, or DRAMs for short. 102 00:07:05,340 --> 00:07:10,760 DRAMs have a very low cost per bit of storage. 103 00:07:10,760 --> 00:07:15,020 The bad news is that the complex sequence of operations required for reading and writing 104 00:07:15,020 --> 00:07:19,699 takes a while, so access times are relatively slow. 105 00:07:19,699 --> 00:07:24,150 And we have to worry about carefully maintaining the charge on the storage capacitor in the 106 00:07:24,150 --> 00:07:27,350 face of external electrical noise. 107 00:07:27,350 --> 00:07:33,360 The really bad news is that the NFET switch isn't perfect and there's a tiny amount leakage 108 00:07:33,360 --> 00:07:37,890 current across the switch even when it's officially off. 109 00:07:37,890 --> 00:07:43,211 Over time that leakage current can have a noticeable impact on the stored charge, so 110 00:07:43,211 --> 00:07:47,850 we have to periodically refresh the memory by reading and re-writing the stored value 111 00:07:47,850 --> 00:07:51,790 before the leakage has corrupted the stored information. 112 00:07:51,790 --> 00:07:57,159 In current technologies, this has to be done every 10ms or so. 113 00:07:57,159 --> 00:07:58,159 Hmm. 114 00:07:58,159 --> 00:08:04,190 Maybe we can get around the drawbacks of capacitive storage by designing a circuit that uses feedback 115 00:08:04,190 --> 00:08:08,639 to provide a continual refresh of the stored information… 116 00:08:08,639 --> 00:08:13,270 Here's a circuit using combinational inverters hooked in a positive feedback loop. 117 00:08:13,270 --> 00:08:18,240 If we set the input of one of the inverters to a digital 0, it will produce a digital 118 00:08:18,240 --> 00:08:20,130 1 on its output. 119 00:08:20,130 --> 00:08:24,680 The second inverter will then a produce a digital 0 on its output, which is connected 120 00:08:24,680 --> 00:08:28,150 back around to the original input. 121 00:08:28,150 --> 00:08:33,320 This is a stable system and these digital values will be maintained, even in the presence 122 00:08:33,320 --> 00:08:37,849 of noise, as long as this circuitry is connected to power and ground. 123 00:08:37,849 --> 00:08:43,620 And, of course, it's also stable if we flip the digital values on the two wires. 124 00:08:43,620 --> 00:08:48,560 The result is a system that has two stable configurations, called a bi-stable storage 125 00:08:48,560 --> 00:08:50,700 element. 126 00:08:50,700 --> 00:08:54,870 Here's the voltage transfer characteristic showing how V_OUT and V_IN of the two-inverter 127 00:08:54,870 --> 00:08:57,200 system are related. 128 00:08:57,200 --> 00:09:02,010 The effect of connecting the system's output to its input is shown by the added constraint 129 00:09:02,010 --> 00:09:04,750 that V_IN equal V_OUT. 130 00:09:04,750 --> 00:09:10,260 We can then graphically solve for values of V_IN and V_OUT that satisfy both constraints. 131 00:09:10,260 --> 00:09:15,520 There are three possible solutions where the two curves intersect. 132 00:09:15,520 --> 00:09:20,330 The two points of intersection at either end of the VTC are stable in the sense that small 133 00:09:20,330 --> 00:09:25,870 changes in V_IN (due, say, to electrical noise), have no effect on V_OUT. 134 00:09:25,870 --> 00:09:32,360 So the system will return to its stable state despite small perturbations. 135 00:09:32,360 --> 00:09:36,080 The middle point of intersection is what we call metastable. 136 00:09:36,080 --> 00:09:40,710 In theory the system could balance at this particular V_IN/V_OUT voltage forever, 137 00:09:40,710 --> 00:09:45,500 but the smallest perturbation will cause the voltages to quickly transition to one of the 138 00:09:45,500 --> 00:09:46,550 stable solutions. 139 00:09:46,550 --> 00:09:51,931 Since we're planing to use this bi-stable storage element as our memory component, we'll 140 00:09:51,931 --> 00:09:56,860 need to figure out how to avoid getting the system into this metastable state. 141 00:09:56,860 --> 00:09:59,550 More on this in the next chapter. 142 00:09:59,550 --> 00:10:03,910 Now let's figure out how to load new values into our bi-stable storage element.