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PROFESSOR In this
problem, we are

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going to take a look at the
timing constraints associated

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with sequential logic circuits.

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We are given a generic
state machine diagram,

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which has two state bits.

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We are also given
the timing parameters

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for the combinational logic
and the state register.

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Using this data we want
to determine the largest

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value for the
register's whole time

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that allows the necessary
timing specifications to be met.

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In order to satisfy the
whole time of the register,

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the input to the register
must remain stable until tHOLD

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after the clock edge.

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The fastest that a new
change can propagate

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to the input of the
register is found

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by taking the sum
of the contamination

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delays along the shortest
path to that input.

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That is [? tCD ?] of the
register plus tCD of the logic.

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So tHOLD must be less than or
equal to tCD of the register

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plus tCD of the logic.

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Plugging in the given
contamination delays,

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we find that tHOLD must be less
than or equal to 0.1 plus 0.2,

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which equals 0.3 nanoseconds.

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What is the smallest
value for the period

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of the clock that will meet
the timing specifications?

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The clock period must be
long enough for the data

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to pass through
the entire circuit

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and be ready and
stable for tSETUP

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before the next period begins.

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The data in this circuit must
propagate through the register

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and the combinational logic.

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So the constraint
on the clock period

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is that tCLOCK has to be
greater than or equal to tPD

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of the register plus
tPD of the logic

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plus tSETUP of the register.

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Plugging in the given
timing parameters,

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we find that tCLOCK must be
greater than or equal to 5

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plus 3 plus 2, which
equals 10 nanoseconds.

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Next, we want to determine
what are the smallest

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setup and whole time
specifications on the input

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in with respect to the
active edge of the clock

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so that we can ensure
that the necessary timing

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specifications are met.

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The IN input must be stable
and valid long enough

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before the rising
clock edge for it

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to propagate through
the combinational logic

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and arrive at the register
in time for it to setup.

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So tSETUP of IN is
greater than or equal

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to tPROPAGATION DELAY
of the LOGIC plus

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tSETUP of the register.

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That equals 3 plus 2,
which equals 5 nanoseconds.

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Once the IN input
becomes invalid,

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the input to the register
will become invalid

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after the contamination
delay of the logic.

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IN must stay valid
long enough to ensure

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that the input to the register
does not become invalid

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before the registers hold time.

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So tHOLD of IN plus
tCD of the LOGIC

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are greater than or equal
to tHOLD of the register.

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This can be rewritten
as tHOLD of IN

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must be greater than
or equal to tHOLD

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of the register minus
tCD of the LOGIC,

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which equals 0.3 minus 0.2.

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And that equals 0.1 nanoseconds.