1 00:00:01,010 --> 00:00:07,210 We are given the combinational circuit shown here consisting of an inverter, an AND gate, 2 00:00:07,210 --> 00:00:10,520 an exclusive OR gate, and a multiplexor. 3 00:00:10,520 --> 00:00:15,510 We are also provided with the contamination and propagation delays for each of the components 4 00:00:15,510 --> 00:00:17,200 in the circuit. 5 00:00:17,200 --> 00:00:22,490 We are then asked to determine the contamination delay and propagation delay for the entire 6 00:00:22,490 --> 00:00:24,060 circuit. 7 00:00:24,060 --> 00:00:29,300 The propagation delay of a circuit is defined as the longest delay that can occur from when 8 00:00:29,300 --> 00:00:33,859 the inputs changed to when the output becomes stable. 9 00:00:33,859 --> 00:00:39,010 In order to calculate the propagation delay of a circuit, we need to identify the path 10 00:00:39,010 --> 00:00:44,780 from input to output whose sum of the propagation delays is the largest. 11 00:00:44,780 --> 00:00:51,260 For this circuit, the longest delay path is through the exclusive or gate and the multiplexor. 12 00:00:51,260 --> 00:01:01,389 The sum of the propagation delay across these 2 gates is 2.1 + 1.5 = 3.6 ns. 13 00:01:01,389 --> 00:01:07,110 The contamination delay of a circuit is defined as the shortest delay from when the inputs 14 00:01:07,110 --> 00:01:11,760 change to when the outputs begin to change, or when the outputs are no longer guaranteed 15 00:01:11,760 --> 00:01:15,360 to be holding their previous stable value. 16 00:01:15,360 --> 00:01:21,230 In order to calculate the contamination delay, we find the path whose sum of the contamination 17 00:01:21,230 --> 00:01:23,220 delays is the least. 18 00:01:23,220 --> 00:01:29,740 For this circuit, the shortest path is from input A through the selector of the multiplexor. 19 00:01:29,740 --> 00:01:34,610 So the contamination delay for this circuit is equal to the contamination delay of the 20 00:01:34,610 --> 00:01:38,840 multiplexor which equals 0.2 ns.